Responsibilities and Achievements

Support 0.25 Embedded-Flash &chi ceramic flat iron 0.18 Flash yield & reliability improvement, my primarily job including:chi ceramic flat iron
1.New Product Start Up. The activities include:-Ensure smooth & speedy new product start up;-Engineering Evaluation onralph lauren polo shirtsralph lauren polo shirts

Reliability & Test evaluation & north face jacketsSplit Analysis;north face jackets-Setup the Bin definitions, sort data to yield management system. Study Probe Flow & Product Knowledge, Setup the FA capability.2.Product Yield Improvement. The activities include:-Closely monitor products yield performances. Generate daily/weekly/monthly report & highlights key issues & areas for yield improvement;-Identified Products’ Probe major failure bins. Extensive study on the failure through Bins to WAT correlation, inline correlation, bitmapping study & FA.;-Perform probe yield analysis on Process Split Experiments;
-Identify process/machine abnormalities through detail bins failures & machine commonality studies;-Interface with various departments on product-related issues.Key achievements:1.Successfully qualified and ramped up 0.25 Embedded-Flash(SST split gate eflash, Chingistek 2T PFlash) to full production; 2.Successfully qualified and ramped up 0.18 Flash (ATMEL, Excel, etc) to production, yield above 94%;
3.Identify the direction of endurance improvement, through lowering the Verase, improve endurance from 30K to ~150K for the split gate Embedded-Flash;4.Identify the baseline serious retention fail, due to NSD/PSD photo resist strip defect, improve sort2 ~20% yield;
5.Identify the serious function failure (program/erase, etc) due to passivation deposition, deposition temperature different with the Metal Anneal cause stress and result in high Resistance of Top Via;6.Identify baseline wafer extreme edge Isb & OLEAK fail (~5%), due to contact open issue (which is for bulk voltage bias), form task force to improve the yield;7.Identify shot dependency Erase/Program fail (~4%), due to small Floating Poly line CD & big overlay, and waferto wafer variance due to 2nd spacer under etch;8.Identify the slow erase (Low Gm) fail due to high Source Rail Resistance & high Source Contact Resistance: (a) improve Rc from fine tune contact CMP & Contact deposition RTA for small key hole, Side Wall etch remained oxide tighten control, (b) improve Source Rail Resistance from reduce Control Gate CD & reduce STI trench depth, (c) reduce source implant ashing defect;9.Identify wafer edge Programming Stress (Bulk stress) fail, improve by enlarging Active CD & Control Gate CD to get high Bulk coupling ratio.10.Identify wafer edge program fail due to Rs_HV NWELL, improve by tighten control STI Depth to lower Rs_HV NWELL;11.Identify high yield degradation due to ACT CD drift to low end causing high program failure; http://boots-n-heels.com/forum
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